Reducing the Effects of Branch Misprediction through Dynamic Heterogeneous Core Scheduling

The magnitude of a branch misprediction penalty is highly dependent on processor pipeline depth. Although longer pipelines may allow higher clock frequency, because less logic is performed in each stage, a fundamental trade-off exists between increased clock speed and accumulated misprediction penalties. Some programs, with easily predictable branches, will perform optimally on long pipelines. The performance of others will be less acceptable on these deep pipelines due to frequent misprediction penalties. These programs would perform optimally on a shorter pipeline achieved through a slower frequency design. Current-generation processors commonly utilize multiple cores to exploit thread-level parallelism. Mainstream production designs consists of either two, four, or more homogeneous cores. Since the cores are identical, the advantages and disadvantages of design decisions are replicated on each. This work considers the sensibility of a heterogeneous design where each core could have independent microarchitecture, within certain feasibility constraints. We create a heterogeneous core design with which we attempt to individually exploit the advantages of multiple design decisions within the same chip. In particular, we investigate the benefits of a processor design with cores of varied pipeline depth and frequency. We believe that through intelligent speculative context swapping between cores, concurrent threads can be optimally allocated among the various heterogeneous cores based on their respective likelihood of branch misprediction. To test this, we consider a dynamic analysis method by which we heuristically determine when such swaps should occur. In order to evaluate our design, we compare our simulation results with those achieved by both an equivalent homogeneous multi-core processor and an idealized heterogeneous design using an oracle to make optimal swapping decisions.